This invention relates to semiconductor memories and more particularly to improved memory cells.
Ever increasing high capacity MOS random access memories (RAM's) are being developed with 64K memories being produced in reasonably large quantities and with 256K memories being produced in limited quantities. U.S. Pat. No. 4,112,575 described memory arrays using single level conductors with memory cells which each have an n-channel MOS transistor with separated drain and source regions and have a capacitor coupled to the source. It also describes memory arrays using dual level conductors with memory cells which each have a single drain/source region and have a capacitor separated from the drain/source region by the channel of the transistor. The described single level conductor memory cell is limited in size by minimum spacing requirements between adjacent conductors. The dual level conductor memory cell can be made physically smaller than the single level conductor memory cell. To insure proper operation of the dual conductor embodiment, it is desirable to extend the substrate portion of the capacitor so that it extends past the top plate of the capacitor and is partly covered by the gate electrode. This adds undesirable capacitive loading onto the gate and can cause variations in charge (logic information) stored in the capacitor as the gate (word line) potential is varied to access the memory cell.
It is desirable to have a one transistor-capacitor MOS memory cell which is more compact than the single conductor one transistor-capacitor memory cell and which has lower gate loading capacitance and less loss of stored charge than the dual conductor one transistor-capacitor memory cell.